1. Field of the Invention
The present invention relates to a method for fabricating titanium silicide contacts.
2. Description of the Prior Art
In general semiconductor fabrications for ASIC devices, the most important factor to be considered is the delay characteristic caused by resistances and capacitances, as compared with fabrications of memory devices.
Major factors affecting such a delay characteristic includes a transistor channel resistance, namely, a saturated current amount, a gate electrode capacitance, concentrations and depths of source and drain regions, a channel length, a channel width, a punchthrough characteristic, a leakage current characteristic, and a junction breakdown voltage characteristic. For realizing superior devices, complemental relationships among the above characteristics should be optimized.
In conventional MOSFET fabrications, the concentrations of source and drain regions should be optimized within a range that the punchthrough characteristic is not degraded, since they affect the effective channel length, so that they have a direct relationship with the current amount. In a device design in a range of not more than micrometers (.mu.), the reliability of devices is considerably dependent on the overlap length between a gate electrode and source/drain regions. This is determined by the source/drain concentrations and a subsequent thermal process, as well as the spacer length.
However, the conventional methods use source and drain regions of high concentration, for an increase in current amount by an adjustment of the effective channel length. They also use TiSi.sub.2 contacts, in order to reduce the contact resistance. In this case, however, the high concentration causes a phenomenon that the TiSi.sub.2 contacts may be partially peeled from the source/drain regions. As a result, there are problems of a simple contact resistance increase and a degradation in reliability. These problems also result in a limitation on a technical flexibility for obtaining characteristics of devices.